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IEEE Design & Test of Computers

IEEE Design & Test of Computers offers original works describing the methods used to design and test electronic product hardware and supportive software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. Topics include IC/module design, low-power design, electronic design automation, design/test verification, practical technology, and standards. IEEE Design & Test of Computers is published by the IEEE Computer Society in technical cosponsorship with the IEEE Circuits and Systems Society.

IEEE Computer Society

  • PrePrint: Reliability Analysis of Small Delay Defects Due to Via Narrowing in Signal Paths
    Open defects in vias are a dominant failure mechanism in nanometer technologies. Their defect probability has increased with the introduction of the copper process, smaller geometries, and via counts on the order of billions for modern integrated circuits. In this work, the aggravated via reliability due to a manufacturing narrowing defect is analyzed.We quantify the reliability risk by estimating the Mean Time to Failure (MTF) as a function of the void size due to narrowing by applying Blacks Law to three possible geometric models for a defective via. Bidirectional current condition in signal paths was considered to estimate electromigration (EM) and self-heating effects. For redundant via structures, the MTF of the good vias was estimated when there is one defective via. Our results show that despite resistive vias showing little disturbance to the signal transmission until severe voiding occurs, the electromigration and self-heating threat are significant even for relatively small initial via voiding. The MTF degradation is significant despite of the bidirectional current condition of signal paths. Hence, our results indicates that new electromigration design rules for signal paths considering the presence of resistive vias are required.



  • PrePrint: SAT-based Analysis of Sensitisable Paths
    Manufacturing defects in nanoscale tech- nologies have highly complex timing behaviour that is also aected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specied length. The resulting tests can be employed e.g. within the framework of adaptive testing. The methodology is based on encoding the problem as an instance of the Boolean Satisability Problem (SAT) and thereby leverages recent advances in SAT-solving technology.



  • PrePrint: Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms
    Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there is a wide family of iterative multimedia algorithms that cannot be executed with satisfactory performance on Multi-Processor Systems-on-Chip or Graphics Processing Units. For this reason, new methods to design custom hardware circuits that exploit the intrinsic parallelism of multimedia algorithms are needed. As a consequence, in this paper, we propose a novel design method for the definition of hardware systems optimized for a particular class of multimedia iterative algorithms. We have successfully applied the proposed approach to several realworld case studies, such as iterative convolution filters and the Chambolle algorithm, and the proposed design method has been able to automatically implement, for each one of them, a parallel architecture able to meet real-time performance (up to 72 frames per second for the Chambolle algorithm), with on-chip memory requirements from 2 to 3 orders of magnitude smaller than the state-of-the art approaches.



  • PrePrint: LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
    Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing failure, which arises from excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase on a portion of the clock tree. This paper proposes a novel layout-aware scan segmentation design scheme called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation) for avoiding shift timing failures. The proposed scheme searches for an optimal combination of scan segments for simultaneous clocking so as to reduce the switching activity in the proximities of clock trees while maintaining the average power reduction effect of the conventional scan segmentation. Experimental results on benchmark circuits have demonstrated the advantage of the LCTI-SS scheme.



  • PrePrint: A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits
    In this paper, we propose an approach to generate high-level test patterns from the arithmetic model of an RTL circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. The current approach has been implemented for a range of small to large benchmark circuits. The results clearly demonstrate that tests generated using the proposed method have achieved high fault coverage for known sequential circuit benchmarks in very short CPU time and minimum memory usage.